Typically, electrical circuits consist of a variety of components, for example, resistors, capacitors, inductors, diodes and transistors. In designing an electrical circuit, the circuit is expected to satisfy certain user-specified requirements. The creation of a complex circuit may involve creation of a topology, component sizing and placement, and also routing of wires that interconnect the circuit's components.
By ‘topology’ is generally meant the number and type of components (e.g., resistors, transistors, diodes). Topology of a circuit may include a list that may include information about connection that exists, in the schematic sense, between any two particular leads of components. By ‘sizing’ is meant assigning values to the circuit's components. By ‘placement’ is meant assignment of each of the circuit's components to a particular physical location on, e.g., a printed circuit board or a silicon wafer. By ‘routing’ is meant assignment of a particular physical location to the interconnection of wires between the leads of the circuit's components.
The exact physical location of each component and wire may affect the overall behavior of all circuits to some extent because electrical components and wires may have interactions with one another based on their physical location. These interactions, generally called parasitic effects, are generally small and may not be important to the performance of ‘simple’ circuits operating at relatively low frequencies. In such cases, parasitic effects may simply be factored out. By ‘parasitic effect’ is meant undesired effect that may be caused by capacitance, resistance, and sometimes inductance, which are introduced by interconnecting wires.
However, parasitic effects may detrimentally affect the performance of a more complex circuit or a circuit operating at relatively high frequencies, for example, at radio frequencies (“RF”). Under such circumstances, it may be impossible to design a practical circuit without factoring in parasitic effects.
Interconnection wirings may affect different circuits in different ways. For example, synchronization is essential for the proper functionality of many digital circuits. However, ‘bad’ wiring routing may ‘force’ the circuit out of synchronization, for example it may undesirably affect the propagation time of an electrical signal between circuit's devices along a certain signal path.
With the ongoing miniaturization of semiconductor devices and integrated circuits into the nanometer domain in past years, the problem of parasitic effects becomes more and more important in circuit design. This is due to the fact that at smaller scales, previously unimportant parasitic effects are now magnified. Therefore, when designing microelectronic circuit, a microelectronics engineer has an additional task, which is to find ways to minimize and overcome these effects while always delivering smaller and faster circuits.
In order to minimize and properly handle parasitic effects, they have to be evaluated first. This is done by use of wire model objects, which are sometimes referred to in the field as ‘delay models’. Wire model objects are useful for timing analysis, which is required to evaluate the functionality of the designed circuit at high operating frequencies in the schematic level. However, traditional time-wise simulation applications are incapable of automatically generating a full-modeled circuit's schema in which essentially every wire and “via” connection is replaced with a corresponding wire model object (“WMO”) and the WMOs are seamlessly ‘fitted’ into the schematic design of the full custom circuit.
Therefore, a need exist for a method for embedding wire model objects into schematic design of full custom circuits, for allowing comprehensive timing analysis in respect thereof.